The method of making a high voltage bipolar transistor during the process of fabricating a CMOS (complementary metal oxide silicon) circuit on an n-substrate.
Bipolar pnp and npn transistors and CMOS field effect transistors (FET's) are normally fabricated in separate processes. For example, vertical pnp transistors are commonly fabricated on a p substrate using the ordinary industrial CMOS process. However, all three types of transistors can be made in one process, BiMOS. A high voltage npn transistor and a high voltage annular PMOS FET with a triple diffused conductive drift region can also be made by adding additional steps to this BiMOS process. This process is described in commonly assigned Patent Application "Bipolar Transistors with High Voltage MOS Transistors in a Single Substrate", Ser. No. 07/878,141, is incorporated herein by reference, and is described in detail below. A result of the basic CMOS process is a vertical pnp bipolar transistor with a breakdown voltage of approximately 20 volts in the inverse direction. However, in some applications such as in the output protection circuit of a high voltage driver, a higher breakdown voltage is required. At the same time, it would be preferred that no additional process steps are required beyond those required by the basic process.